Power MOSFETs typically consist of a pattern of MOSFET cells that are arrayed on the surface of a semiconductor chip. Each cell includes a source region and a body region having opposite conductivity types. At the boundary of the cells a gate overlies the semiconductor material and controls the flow of current through a channel that is formed in the body regions at the surface of the semiconductor material. The gate is electrically isolated from the semiconductor by an insulating layer, typically an oxide. The source and body regions are often formed in a relatively lightly doped epitaxial layer that is formed on top of a more heavily doped substrate. When the MOSFET is turned on, current flows in a path which extends from the source region and through the channel and the epitaxial layer to the substrate, which functions as the drain. Depending on whether the device is an N-channel or P-channel MOSFET, the current (as defined by convention as the flow of positive charges) either flows from the source to the drain (P-channel) or from the drain to the source (N-channel). Actually electrons flow from the negative potential to the more positive potential in N-channel devices. The source and drain are normally contacted by metal layers on opposite surfaces of the chip, although in quasi-vertical devices the drain contact is on the same side of the device as the source contact, and a sinker region having the same conductivity type as the drain extends from the surface to the drain. In most devices, the metal layer which contacts the source also makes contact with the body region. Shorting the source to the body prevents the parasitic bipolar transistor formed by the source (emitter), body (base), and drain (collector) from tuning on.
A cross-sectional view of a typical vertical planar DMOSFET (i.e., double-diffused MOSFET) is shown in FIG. 1. DMOSFET 10 contains a source region 100, a body region 102, a drain region 104, and a gate 106. Source region 100 and body region 102 are formed in an epitaxial (epi) layer 108 which overlies a substrate 110. A metal layer 112 contacts source region 100 and body region 102, a heavily doped body contact region 114 facilitating contact with the body region 102. A metal layer 116 contacts the drain region 104. The gate 106 is separated from the surface of the epi layer 108 by a gate oxide layer 117. Channel regions 118 are located in the body region 102 near the surface of the epi layer 108.
The pattern is repeated in epi layer 108, and FIG. 1 shows a portion of a neighboring source region 100A, body region 102A and channel region 118A. A single section of the gate 106 controls the flow of current (denoted by the arrows) through both of the channel regions 118 and 118A. The currents from channel regions 118 and 118A come together in a region of the epi layer 108 between the body regions 102 and 102A that is sometimes referred to as the "JFET" region, denoted by numeral 124 in FIG. 1.
Together the sections of gate 106 form a grid or stripe pattern, with the gate sections connected as a single electrode.
While MOSFET 10 is shown as an N-channel device, a similar P-channel device has the same structure with the polarities of the various regions reversed (P for N, N for P).
A single "cell" of MOSFET 10 can be defined as having a width W that extends between a line 120 at the center of one section of gate 106 to a line 122 at the center of a another section of gate 106 on the opposite side of the source region 100 and body region 102. The cell can have various shapes and can be either in the form of a closed polygon (e.g., a square or hexagon) or a longitudinal strip.
Generally speaking, the current-carrying capacity of the MOSFET can be increased (and the on-resistance reduced) by packing more cells into a unit area of the surface of the device. This increases the total perimeter of the cells and the total channel "width" through which the current may flow. The packing density of the cells is a function of the cell width W.
There are limitations, however, on reducing W. The width of the JFET region 124 (shown as d.sub.1) can be reduced only to certain point without increasing current-crowding in the JFET region 124 and increasing the on-resistance of the device. The length of the channel, shown as d.sub.2 cannot be reduced without risking punchthrough breakdown (an undesirable condition where the channel becomes totally depleted and current flows independently of the gate bias).
What remains is the possibility of reducing the distance between the sections of gate 106, shown as d.sub.3. The problem is to insure that a separation is maintained between gate 106 and metal layer 112. The gate 106 and the metal layer 112 are normally formed by photolithographic processes which involve masking and etching. FIG. 2, for example, shows a mask opening that is used to form an opening in a BPSG layer 200 for the source/body contact in a MOSFET 20. The distance d.sub.4 represents the separation between the gate 206 and the (future) contact.
Photolithographic processes are subject to errors in the lateral sizes and positioning of the elements defined. In these circumstances, the following formula expresses the minimum permissible design spacing between gate 106 and metal layer 112: EQU GateToMetalSpacing.sub.min =.DELTA.CD.sub.gate.sup.2 +.DELTA.CD.sub.contact.sup.2 +MA.sub.gate/contact.sup.2 +L
where .DELTA.CD.sub.gate is the is the variation in the critical dimension of the gate 106, .DELTA.CD.sub.contact is the variation in the critical dimension of the contact (metal layer 112), and MA.sub.gate/contact is the potential misalignment between the gate and contact. If this separation is not maintained, there is an unacceptable risk that the gate will be shorted to the metal contact, and the MOSFET will permanently disabled. In a low cost production process a projection aligner or 1X stepper would be used and the variations in the critical dimension and potential misalignment would be relatively large. These values can be reduced by using, for example, a 5X reduction stepper, but this increases the cost significantly. The distance d.sub.3 is typically from 0.5.mu. to 1.0.mu. , and only with very expensive equipment can d.sub.3 be reduced much below 0.5.mu. .
U.S. Pat. No. 5,476,803 to Lui teaches the use of a spacer oxide on the side walls of the gate region in a lateral MOSFET. However, although Lui notes that the spacer oxide may be used to reduce the overall size of the semiconductor device, Lui is primarily concerned with problems specific to lateral devices, i.e., altering the doping diffusions of the drain to reduce the parasitic capacitance and resistance of the lateral device. Moreover, Lui teaches that the width of the spacer oxide regions would be "somewhat diminished, and thus would not prevent the transistor . . . from shorting" unless a "pad oxide layer" of "substantial thickness" remains on the top of the gate electrode.
Thus there is a clear need for an economical way of reducing the MOSFET cell dimension in a vertical planar device, and particularly the distance between the gate segments.